Treffer 61 - 80 von 127

61

Estado del arte en las metodologías de diseño de circuitos digitales asíncronos
Rubén Darío Nieto-Londoño ; Álvaro Bernal Noreña
INGENIERÍA Y COMPETITIVIDAD. 7:84-91

Modelos de retardo no ac... Diseño digital asíncrono... Modeling and Control of... Real-Time Scheduling in... System-Level Design FOS: Humanities
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62

Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
Monica Pereira ; Luigi Carro
International Journal of Reconfigurable Computing, Vol 2011 (2011)

Parallel computing Computer engineering. Co... Computer Networks and Co... Geometry 02 engineering and techn... MPSoC
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63

Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures
Ktata, Ismail ; Ghaffari, Fakhreddine ; Granado, Bertrand ; et al.
International Journal of Reconfigurable Computing, Vol 2011 (2011)

[INFO.INFO-AR] Computer... Computer engineering. Co... Artificial intelligence Dynamic priority schedul... [INFO.INFO-TS] Computer... Robot
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64

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices
Ikbel Belaid ; Fabrice Muller ; Maher Benjemaa ; et al.
International Journal of Reconfigurable Computing, Vol 2011 (2011)

Parallel computing Computer engineering. Co... Computer Networks and Co... Dynamic Reconfiguration 02 engineering and techn... Control reconfiguration
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65

Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems
Diana Göhringer ; Jonathan Obie ; André L. S. Braga ; et al.
International Journal of Reconfigurable Computing, Vol 2011 (2011)
International journal of reconfigurable computing, 2011, Art.Nr. 985931

ddc:620 Parallel computing Computer engineering. Co... 0209 industrial biotechn... Virtex Chip
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66

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment
Mateus Beck Rutzig ; Antonio Carlos Schneider Beck ; Felipe L Madruga ; et al.
International Journal of Reconfigurable Computing, Vol 2011 (2011)

Parallel computing Exploit Computer engineering. Co... Thread (computing) Artificial intelligence Computer Networks and Co...
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67

A Reconfigurable System Approach to the Direct Kinematics of a 5D.o.fRobotic Manipulator
Diego F. Sánchez ; Daniel M. Muñoz ; Carlos H. Llanos ; et al.
International Journal of Reconfigurable Computing, Vol 2010 (2010)

Computer engineering. Co... 0209 industrial biotechn... PowerPC Cinemática das máquinas... Dynamic Reconfiguration 02 engineering and techn...
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68

Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments
L. Costa ; Alisson V. Brito ; Tiago Nascimento ; et al.
IFIP Advances in Information and Communication Technology ISBN: 9783319900223

Interface (matter) Artificial intelligence History Robot Bridge (graph theory) Real-Time Simulation Tec...
Buch
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69

A novel method for on-chip debugging based on RISC-V processor
Shan Gao ; Dehua Wu ; Wan'ang Xiao ; et al.
MATEC Web of Conferences, Vol 355, p 03055 (2022)

Parallel computing Instruction set Interface (matter) risc-v processor Computer Networks and Co... Networks on Chip
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70

Formal Analysis of Fault-tolerant Algorithm in the Time-triggered Architecture
Zibouda Aliouat ; Makhlouf Aliouat ; Batouche Chawki
Journal of Computer Science. 3:28-34

Computer Networks and Co... Real-Time Scheduling in... Fault Tolerance Fault tolerance 02 engineering and techn... Reconfigurable Computing...
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71

From Design Specification to SystemC
Mohamed T. Kimour ; Rachid Boudour
Journal of Computer Science. 2:201-204

Code (set theory) Artificial intelligence Executable Electronic system-level... System-Level Design Set (abstract data type)
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72

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)
Kaoutar Aamali ; Abdelhakim Alali ; Mohamed Sadik ; et al.
E3S Web of Conferences, Vol 229, p 01025 (2021)

Computer Networks and Co... System-level simulation Chip System-Level Design Epistemology 02 engineering and techn...
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73

Memory Utilization and Machine Learning Techniques for Compiler Optimization
A. V. Shreyas Madhav ; Siddarth Singaravel ; Karmel Arockiasamy
ITM Web of Conferences, Vol 37, p 01021 (2021)

FOS: Computer and inform... Parallel computing Loop optimization Compiler Information technology 02 engineering and techn...
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74

Design of Efficient Pipelined Router Architecture for 3D Network on Chip
Bouraoui Chemli ; Abdelkrim Zitouni ; A. Coelho ; et al.
International Journal of Advanced Computer Science and Applications. 8

Computer Networks and Co... Networks on Chip Three-Dimensional Integr... Arbiter 02 engineering and techn... 7. Clean energy
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75

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC
R.B. Salem ; Yahia Salah ; Imed Bennour ; et al.
International Journal of Advanced Computer Science and Applications. 8

Parallel computing Computer Networks and Co... Virtex Multiprocessing 02 engineering and techn... MPSoC
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76

A New Network on Chip Design Dedicated to Multicast Service
Chatmen, Mohamed Fehmi ; Baganne, Adel ; Rached, Tourki ; et al.
International Journal of Advanced Computer Science and Applications. 7

Computer Networks and Co... Networks on Chip Economics Unicast 02 engineering and techn... Latency (audio)
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77

Scheduling on Heterogeneous Multi-core Processors Using Stable Matching Algorithm
MUHAMMAD ADNAN REHMAN ; Muhammad Asfand-e-yar
International Journal of Advanced Computer Science and Applications. 7

Parallel computing Many core Computer Networks and Co... 02 engineering and techn... Quantum mechanics 7. Clean energy
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78

Review of Network on Chip Routing Algorithms
Khurshid Ahmad ; Muhammad Athar Javed Sethi
EAI Endorsed Transactions on Context-aware Systems and Applications, Vol 7, Iss 22 (2020)

Parallel computing Computer Networks and Co... Networks on Chip system on chip Multiprocessing Link-state routing proto...
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79

Consideration of the reconfigurable aspect in evaluating predictive reliability of mechatronic system
Nabil Ben Said Amrani ; Driss Sarsri ; Mihaela Barreau ; et al.
MATEC Web of Conferences, Vol 286, p 05002 (2019)

Reconfigurable Manufactu... Predictive Reliability 02 engineering and techn... Mécatronique 01 natural sciences Industrial and Manufactu...
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80

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface
Shih‐Lun Chen ; Tsun‐Kuang Chi ; Min‐Chun Tuan ; et al.
Electronics
Volume 9
Issue 9

Parallel computing Interface (matter) Phase-Locked Loops in Hi... SPI Chip digital signal process
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