• Suche: "Reconfigurable Computing Systems and Design Methods"

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1

A Multidimensional Approach for Formal Modeling and Analyzing Medical Cyber-Physical Systems
Ayoub Bouheroum ; Djamel Benmerzoug ; Sofiane Mounine Hemam ; et al.
Engineering, Technology & Applied Science Research. 15:20211-20221

Cyber-Physical Systems 9. Industry and infrastr... Modeling and Control of... Platform-Based Design System-Level Design Security Challenges in S... …
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2

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
Youwei Xiao ; Zizhang Luo ; Kexing Zhou ; et al.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays. :211-222

Parallel computing Cement Computer hardware Low-Power VLSI Circuit D... Reconfigurable Computing... Computer science …
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3

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition
Liqiang Lu ; Zizhang Luo ; Size Zheng ; et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43:1177-1190

Parallel computing Computer Networks and Co... Latency (audio) 7. Clean energy Multicore Architectures 11. Sustainability …
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4

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V
Minh Vo
International Journal of Electrical and Electronics Research. 12:238-246

Instruction set Clock skew Jitter 02 engineering and techn... Quantum mechanics 7. Clean energy …
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5

CTLA: Compressed Table Look up Algorithm for Open Flow Switch
Veeramani Sonai ; Indira Bharathi ; Muthaiah Uchimucthu ; et al.
IEEE Open Journal of the Computer Society, Vol 5, Pp 73-82 (2024)
IEEE Open Journal of the Computer Society (OJ-CS)

Table (database) Computer Networks and Co... Geometry Information technology 7. Clean energy Distributed Grid Computi... …
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6

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation
Kexing Zhou ; Yun Liang ; Yibo Lin ; et al.
56th Annual IEEE/ACM International Symposium on Microarchitecture. :180-193

Parallel computing Computer Networks and Co... Flexibility (engineering... Graph Theoretical computer sci... Functional verification …
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7

Parallel FPGA Routers With Lagrange Relaxation
Rohit Agrawal ; Kapil Ahuja ; Dhaarna Maheshwari ; et al.
IEEE Access, Vol 11, Pp 121786-121799 (2023)

ddc:004 Artificial intelligence LP Heuristic Social psychology 7. Clean energy …
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8

Supporting single and multi-core resource access protocols on object-oriented RTOSes
Lucas Matheus dos Santos ; Giovani Gracioli ; Tomasz Kloda ; et al.
Design Automation for Embedded Systems. 27:31-50

Economics 0102 computer and inform... 02 engineering and techn... Multiprocessor Schedulin... 01 natural sciences Priority ceiling protoco... …
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9

Scheduling and Energy Savings for Small Scale Embedded FreeRTOS-based Real-Time Systems
Gessé Oliveira ; George Lima
Design Automation for Embedded Systems. 27:3-29

Dynamic priority schedul... 0102 computer and inform... 02 engineering and techn... Fixed-priority pre-empti... Multiprocessor Schedulin... 01 natural sciences …
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10

A Power-Aware Real-Time System for Multi-Video Treatment on FPGA with Dynamic Partial Reconfiguration and Voltage Scaling
Lilia Kechiche ; Lamjed Touil ; Mehdi Jemai ; et al.
Engineering, Technology & Applied Science Research. 12:8996-9004

Computer Networks and Co... Dynamic Reconfiguration Advancements in Video Co... Dynamic demand 02 engineering and techn... Control reconfiguration …
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11

DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization
Ibtissem Wali ; Amina Kessentini ; Mohamed Ali Ben Ayed ; et al.
International Journal of Recent Technology and Engineering (IJRTE). 10:24-31

Artificial intelligence Scalable Compression Advancements in Video Co... Digital signal processor 7. Clean energy Quantization (signal pro... …
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12

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
Romina Molina ; Verónica Gil-Costa ; M.L. Crespo ; et al.
IEEE Access, Vol 10, Pp 90429-90455 (2022)

Metric (unit) POWER CONSUMPTION System-Level Design system on chip (SoC) 02 engineering and techn... design space exploration …
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13

An Ultra Fast Settling and Low Area Bit Synchronizer Architecture
Amitava Ghosh ; Anindya Sundar Dhar
Analog Integrated Circuits and Signal Processing. 123

Computer network Wireless Sensor Networks... Computer Networks and Co... Transmitter Computer hardware Latency (audio) …
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14

Towards Test-Driven Development for FPGA-Based Modules Across Abstraction Levels
Julián Caba ; Fernando Rincón ; Jesús Barba ; et al.
IEEE Access, Vol 9, Pp 31581-31594 (2021)
IEEE Access

FPGA-Based Emulation Real-Time Simulation Tec... System-Level Design 02 engineering and techn... Engineering Design flow …
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15

Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems
Denis S. Loubach ; Ricardo Bonna ; George Ungureanu ; et al.
IEEE Access, Vol 9, Pp 156337-156360 (2021)

Executable Embedded systems Dynamic Reconfiguration System-Level Design Epistemology 02 engineering and techn... …
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16

Industrial robot arm controller based on programmable System-on-Chip device
Vo Duy Cong
FME Transactions, Vol 49, Iss 4, Pp 1025-1034 (2021)

0209 industrial biotechn... Microcontroller Flexibility (engineering... ARM architecture 02 engineering and techn... Sensor-Based Robot Syste... …
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17

Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique
Eng Keong Teh ; Mohamad Adzhar Md Zawawi ; Mohamed Fauzi Packeer Mohamed ; et al.
IEEE Access, Vol 9, Pp 14816-14835 (2021)

Artificial intelligence Chip Clock skew Heuristic Jitter Skew …
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18

An optimizing technique for using MATLAB HDL coder
Somaya Kayed ; Ghada Elsayed
Bulletin of the National Research Centre, Vol 47, Iss 1, Pp 1-8 (2023)

Parallel computing MATLAB Science Biomedical Engineering Chip Set (abstract data type) …
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19

Hardware Optimization for Effective Switching Power Reduction during Data Compression in GOLOMB Rice Coding
R. Sakthivel ; Vijayalakshmi Chintamaneni ; Suman Tenali ; et al.

Parallel computing Artificial intelligence Image compression Computer Networks and Co... Geometry Golomb coding …
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20

Preemption-Aware Allocation, Deadline Assignment for Conditional DAGs on Partitioned EDF
Houssam-Eddine Zahaf ; Giuseppe Lipari ; Smaïl Niar ; et al.
2020 IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). :1-10

Parallel computing Execution time Computer Networks and Co... Set (abstract data type) Multiprocessing 02 engineering and techn... …
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