• Suche: "field-programmable gate array"

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1

Origami : L'art du pliage appliqué à l'accélération des CNNs sur FPGA
Pradels, Léo ; Garcia, Rémi ; Filip, Silviu-Ioan ; et al.
GRETSI 2025 - Groupe de Recherche et d'Etudes de Traitement du Signal et des Images. :1-4

Strasboug, France Design space exploration... Integer linear program I... FPGA - field-Programmabl... DNN accelerators [INFO]Computer Science [...
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2

Power Consumption Analysis for Reverse Engineering Digital Modulation: A Novel Approach to Physical Layer Attacks on Communication Systems
Pareja, Pablo ; Nasser, Yehya ; Masmoudi, Ahmed ; et al.
European Interdisciplinary Cybersecurity Conference, Jun 2025, Rennes, France

Rennes, France Physical Layer Security Side-channel attack (SCA... HDL Field-Programmable Gate... Boosted Trees …
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3

TOWARDS REAL-TIME AURALIZATION ON FPGAS
VERS UNE AURALISATION EN TEMPS RÉEL SUR FPGA
Jeunehomme, Rémi ; Michon, Romain ; Risset, Tanguy ; et al.
SMC 2025 - 22nd Sound and Music Computing Conference, University of Music and Performing Arts, Graz, Jun 2025, Gratz, Austria. ⟨10.5281/zenodo.15836298⟩

Gratz, Austria Audio FFT FPGA - field-Programmabl... [INFO]Computer Science [... [INFO.INFO-ES]Computer S... …
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4

Scalable Hydrodynamics on multiple Field-Programmable Gate Arrays (FPGAs)
Mordant, François-Xavier ; Prouveur, Charles ; Tremblin, Pascal ; et al.
SC Workshops '25: Workshops of the International Conference for High Performance Computing. :1832-1841

St Louis MO USA, United... Energy efficiency Weak scaling Scalability Hydrodynamics Field Programmable Gate... …
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5

ModNEF : An open source Spiking Neural Network Emulator for FPGA
Saulquin, Aurélie ; Centre de Recherche en Informatique, Signal et Automatique de Lille - UMR 9189 (CRIStAL) ; Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS) ; et al.
PEPR IA Days, Mar 2025, Gif-sur-Yvette, France

Gif-sur-Yvette, France Embeded system Hardware Accelerator Spiking Neural Network FPGA - field-Programmabl... [INFO.INFO-AR]Computer S... …
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6

Contributions aux méthodologies et outils de conception des System-on-Chip : capture applicative, architecture et sécurité
Le Lann, Jean-Christophe ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique) ; et al.
Ingénierie assistée par ordinateur. Université de Bretagne Occidentale, 2025

ESL design Software engineering High-level synthesis HLS System-on-Chip SoC EDA Modélisation logicielle …
Report
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7

Hardware Integration of a Neural Network onto FPGA and its Application to Sound Source Localization
Holmes, Emily ; Loubet, Gaël ; Danès, Patrick ; et al.

Nancy, France Artificial Neural Networ... Field-Programmable Gate... Sound Source Localizatio... Algorithm-Architecture A... Embedded Artificial Inte... …
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8

Impact of High-Level-Synthesis on Reliability of Neural Network Hardware Accelerators
Traiola, Marcello ; Fernandes Dos Santos, Fernando ; Sentieys, Olivier ; et al.
NSREC 2023 - IEEE Nuclear & Space Radiation Effects Conference. :1-5

Kansas City (US), United... FPGA - field-Programmabl... Neural networks Reliability Radiations High-Level Synthesis …
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9

Hardware-Assisted Range Image Generation for LiDAR Point Clouds
Fábio Oliveira ; Vitor Ferreira ; Sandro Pinto ; et al.
IEEE Sensors Letters. 9:1-4

Light Detection and Rang... Range image Field-programmable gate...
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10

Integrating Bio-inspired Optimization with FPGA for Enhanced PID Control in Robotics
Pastrana Triana, Mario Andrés ; Souza Santana, Mateus ; Mendoza Peñaloza, Jose Alfredo ; et al.
Arabian Journal for Science and Engineering. :1-23

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11

Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder
Datta, Debarshi ; Naskar, Mrinal Kanti
National Academy Science Letters. :1-4

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12

Discrete Time-Delay Memristive Chaotic Map and Its Applications
Liu, Wenhao ; Sun, Kehui ; Wang, Huihai ; et al.
Nonlinear Dynamics: An International Journal of Nonlinear Dynamics and Chaos in Engineering Systems. 113(24):33953-33968

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13

FPGA-Based Method for Automated Design of Neural Network Controllers
Shymkovych, V. M. ; Doroshenko, A. Yu. ; Kravets, P. I. ; et al.
Cybernetics and Systems Analysis. :1-16

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14

Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline
Ling, Ming ; Tang, Shidi ; Chen, Ruiqi ; et al.
Frontiers of Information Technology & Electronic Engineering. 26(11):2215-2230

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15

Optimized FFT Designs for High-Performance LTE and 5G Networks
Khan, Daud ; Jan, Latif ; Zafar, Mohammad Haseeb
Arabian Journal for Science and Engineering. 50(21):17555-17574

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16

Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators
Traiola, Marcello ; dos Santos, Fernando Fernandes ; Rech, Paolo ; et al.
IEEE Transactions on Nuclear Science. :1-9

Neural Networks High-Level Synthesis HLS FPGA - field-Programmabl... Reliability Radiation testing [INFO]Computer Science [... …
Zeitschrift
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17

Maximizing OFDM Performance Through Real Time Adaptivity
Blümm, Christian

Flugkörper Field programmable gate... Digitale Subtraktionsang... Adaptive Radio OFDM Technology, Engineering,...
E-Book
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18

Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT
P Surya ; C Arunachalaperumal ; S Dhilipkumar
Measurement Science Review, Vol 25, Iss 3, Pp 134-140 (2025)

bit inversion technique look-up table field programmable gate... low power fast fourier t... 5g application QA1-939 …
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19

Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs
Madani Bachir ; Azzaz Mohamed Salah ; Sadoudi Said ; et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 44:2168-2180

Finite field arithmetic cryptography Modular adder Field Programmable Gate... Ripple carry adder
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20

Enhanced security framework for medical data embedding based on octonionic steganographic transforms and FPGA-accelerated integrity verification
Mohamed Amine Tahiri ; Ilham Karmouni ; Ismail Mchichou ; et al.
Alexandria Engineering Journal, Vol 125, Iss, Pp 480-495 (2025)

Signal processing Steganography TA1-2040 Engineering (General). C... Image registration Field-programmable gate...
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