Result: Automated solutions for CNN model acceleration on mobile platforms.

This paper presents an FPGA-based convolutional neural network (CNN) accelerator designed to enhance computational efficiency and flexibility for resource-constrained platforms. While FPGAs offer high energy efficiency and adaptability, large-scale CNN deployments face challenges such as computational intensity, diverse kernel sizes, and hardware limitations. To address these issues, we propose an accelerator optimized across four convolution loop dimensions, ensuring efficient resource utilization and streamlined data transmission. Our architecture incorporates three key innovations: (1) Loop-optimized computation framework, which dynamically balances parallelism between inner and outer loops, maximizing data reuse and preventing performance bottlenecks; (2) Customized data layout and memory management, mitigating bandwidth limitations and ensuring high computational efficiency under varying workloads; (3) Automated parameter optimization, integrating reinforcement learning with Python-based search algorithms to explore design configurations, optimizing performance for specific applications. The accelerator is validated on ZCU111 and ZCU102 FPGA platforms using ResNet-50, ResNet-152, and VGG-16. Results show that 69.9 % of computations achieve ≥80 % efficiency, 47.1 % surpass 90 %, and 19.2 % exceed 95 % efficiency, demonstrating superior performance over prior FPGA implementations. Compared to existing designs, our approach achieves a 64.0 % increase in efficiency and a 36.5 % boost in throughput, while maintaining flexibility across network architectures. These findings highlight the potential of automated optimization techniques in FPGA-based CNN acceleration. [ABSTRACT FROM AUTHOR]