Wang, B., Ma, S., Zhu, G., Yi, X., & Xu, R. (2022). A novel systolic array processor with dynamic dataflows. Integration: The VLSI Journal, 85, 42-47. https://doi.org/10.1016/j.vlsi.2022.03.002

WANG, Bo, MA, Sheng, ZHU, Guoyi, YI, Xiao und XU, Rui, 2022. A novel systolic array processor with dynamic dataflows. Integration: The VLSI Journal. 1 Juli 2022. Vol. 85, , p. 42-47. DOI 10.1016/j.vlsi.2022.03.002.

Wang, B., S. Ma, G. Zhu, X. Yi, und R. Xu. „A Novel Systolic Array Processor With Dynamic Dataflows.“. Integration: The VLSI Journal, Bd. 85, Juli 2022, S. 42-47, https://doi.org/10.1016/j.vlsi.2022.03.002.

Wang, Bo/Ma, Sheng/Zhu, Guoyi/Yi, Xiao/Xu, Rui: A novel systolic array processor with dynamic dataflows., Integration: The VLSI Journal 2022, 42-47.

Wang, B., Ma, S., Zhu, G., Yi, X. und Xu, R. (2022), „A novel systolic array processor with dynamic dataflows.“, Integration: The VLSI Journal, Vol. 85, S. 42-47.