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Treffer: The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation.

Title:
The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation.
Authors:
Goos, G., Hartmanis, J., Barstow, D., Brauer, W., Brinch Hansen, P., Gries, D., Luckham, D., Moler, C., Pnueli, A., Seegmüller, G., Stoer, J., Wirth, N., Leeser, Miriam, Brown, Geoffrey, Martin, Alain J.1
Source:
Hardware Specification, Verification & Synthesis: Mathematical Aspects. 1990, p244-259. 16p.
Database:
Supplemental Index

Weitere Informationen

We have designed the first delay-insensitive microprocessor. It is a 16-bit, RISC-like architecture. The version implemented in 1.6 micron SCMOS runs at 18 MIPS. The chips were found functional on "first silicon." The processor was first specified as a sequential program, which was then transformed into a concurrent program so as to pipeline instruction execution. The circuits were derived from the concurrent program by semantics-preserving program transformation. [ABSTRACT FROM AUTHOR]