Treffer: Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic Force Microscopy Nanolithography

Keywords: Local anodic oxidation (LAO); Silicon-on-insulator (SOI); Atomic force microscope (AFM), Double gate (DG) and Single gate (SG) Junction-less silicon nanowire transistor (JLSNWT). Abstract. In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (10 5 cm -3 ) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized Online: 2013-01-25 ISSN: 2234-9871, Vol. 3, pp 93-113 doi:10.4028/www.scientific.net/NH.3.93 © 2013 This is an open access article under the CC-BY 4.0 license (https://creativecommons.org/licenses/by/4.0/) by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode. Nano Hybrids