Treffer: FPGA-based modelling unit for high speed lossless arithmetic coding
Title:
FPGA-based modelling unit for high speed lossless arithmetic coding
Source:
FPL 2001 : field-programmable logic and applications (Belfast, 27-29 August 2001)Lecture notes in computer science. :643-647
Publisher Information:
Berlin: Springer, 2001.
Publication Year:
2001
Physical Description:
print, 8 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Codage binaire, Binary coding, Codificación binaria, Codage, Coding, Codificación, Code arithmétique, Arithmetic code, Código aritmético, Compression donnée, Data compression, Compresión dato, Conception circuit, Circuit design, Concepción circuito, Grande vitesse, High speed, Gran velocidad, Parallélisme, Parallelism, Paralelismo, Réseau porte programmable, Field programmable gate array, Red puerta programable, Unité arithmétique, Arithmetic unit, Unidad aritmética
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Electronic and Electrical Engineering Department, Institut für Grundlagen der Elektrotechnik und Elektronik (IEE) TU Dresden, 01062 Dresden, Germany
Electronic Systems Design Group, Loughborough University, Loughborough, Leics., LE11 3TU, United Kingdom
Dept. of Computer Science Engineering & Applications, Regional Engineering College, Rourkela - 769 008, Orissa, India
Electronic Systems Design Group, Loughborough University, Loughborough, Leics., LE11 3TU, United Kingdom
Dept. of Computer Science Engineering & Applications, Regional Engineering College, Rourkela - 769 008, Orissa, India
ISSN:
0302-9743
Rights:
Copyright 2001 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.1019989
Database:
PASCAL Archive
Weitere Informationen
This paper presents a hardware implementation of an adaptive modelling unit for parallel binary arithmetic coding. The presented model combines the advantages of binary arithmetic coding where the coding process is simplified, with the benefits of multi-alphabet arithmetic coding where any type of data can be compressed. The modelling unit adopts a simple method to store and modify the information, making it able to process 8 bits per clock cycle and to increase substantially the arithmetic coding speed. This model has been implemented in an A500K130 ProASIC FPGA and offers a throughput of 256 Mbits/s.