• Busy-wait barrier synchronizat...

Treffer: Busy-wait barrier synchronization using distributed counters with local sensor

Title:
Busy-wait barrier synchronization using distributed counters with local sensor
Authors:
GUANSONG ZHANG, MARTINEZ, Francisco, TAL, Arie, BLAINEY, Bob
Source:
OpenMP shared memory parallel programming (Toronto ON, 26-27 June 2003)Lecture notes in computer science. :84-98
Publisher Information:
Berlin: Springer, 2003.
Publication Year:
2003
Physical Description:
print, 13 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Généralités, General, Intelligence artificielle, Artificial intelligence, Reconnaissance des formes. Traitement numérique des images. Géométrie algorithmique, Pattern recognition. Digital image processing. Computational geometry, Reconnaissance et synthèse de la parole et du son. Linguistique, Speech and sound recognition and synthesis. Linguistics, Antémémoire, Cache memory, Antememoria, Augmentation, Increase, Aumentación, Implémentation, Implementation, Implementación, Latence, Latency, Latencia, Multiprocesseur, Multiprocessor, Multiprocesador, Nombre, Number, Número, Programmation parallèle, Parallel programming, Programación paralela, Reconnaissance forme, Pattern recognition, Reconocimiento patrón, Réduction système, System reduction, Reducción sistema, Réseau capteur, Sensor array, Red sensores, Synchronisation, Synchronization, Sincronización, Système réparti, Distributed system, Sistema repartido, Traitement image, Image processing, Procesamiento imagen, Traitement parole, Speech processing, Tratamiento palabra
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
IBM Toronto Lab, Toronto ON, L6G 1C7, Canada
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=15691719
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.15691719
Database:
PASCAL Archive

Weitere Informationen

Barrier synchronization is an important and performance critical primitive in many parallel programming models, including the popular OpenMP model. In this paper, we compare the performance of several software implementations of barrier synchronization and introduce a new implementation, distributed counters with local sensor, which considerably reduces overhead on POWER3 and POWER4 SMP systems. Through experiments with the EPCC OpenMP benchmark, we demonstrate a 79% reduction in overhead on a 32-way POWER4 system and an 87% reduction in overhead on a 16-way POWER3 system when comparing with a fetch-and-add implementation. Since these improvements are primarily attributed to reduced L2 and L3 cache misses, we expect the relative performance of our implementation to increase with the number of processors in an SMP and as memory latencies lengthen relative to cache latencies.