• High-speed event-driven RTL co...

Treffer: High-speed event-driven RTL compiled simulation

Title:
High-speed event-driven RTL compiled simulation
Authors:
KUPRIYANOV, Alexey, HANNIG, Frank, TEICH, Jürgen
Source:
Computer systems : architectures, modeling, and simulation (Samos, 21-23 July 2003 & 19-21 July 2004)Lecture notes in computer science. :519-529
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 14 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture circuit, Circuit architecture, Arquitectura circuito, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Circuit ET, AND circuit, Circuito Y, Compilateur, Compiler, Compilador, Décomposition graphe, Graph decomposition, Descomposición grafo, Grande vitesse, High speed, Gran velocidad, Niveau transfert registre, Register transfer level, Registro RTL, Optimisation, Optimization, Optimización, Simulateur, Simulator, Simulador, Simulation ordinateur, Computer simulation, Simulación computadora, Sous graphe, Subgraph, Subgrafo, Système réactif, Reactive system, Sistema reactivo
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16075673
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16075673
Database:
PASCAL Archive

Weitere Informationen

In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part of our BUILDABONG [7] framework, which aims at architecture and compiler co-generation for special purpose processors. The main focus of the paper is on the transformation of a given architecture's circuit into a graph and applying on it an essential graph decomposition algorithm to transform the graph into subgraphs denoting the minimal subsets of sequential elements which have to be reevaluated during each simulation cycle. As a second optimization, we present a partitioning algorithm, which introduces intermediate registers to minimize the number of evaluations of combinational nodes during a simulation cycle. The simulator's superior performance compared to an existing commercial simulator is shown. Finally, we demonstrate the pertinence of our approach by simulating a MIPS processor.