Treffer: An optimized flow for designing high-speed, large-scale CMOS ASIC socs
Title:
An optimized flow for designing high-speed, large-scale CMOS ASIC socs
Source:
Computer systems : architectures, modeling, and simulation (Samos, 21-23 July 2003 & 19-21 July 2004)Lecture notes in computer science. :98-107
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 9 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture ordinateur, Computer architecture, Arquitectura ordenador, Circuit à la demande, Custom circuit, Circuito integrato personalizado, Grande vitesse, High speed, Gran velocidad, Langage description matériel informatique, Hardware description languages, Méthode formelle, Formal method, Método formal, Spectrométrie, Spectrometry, Espectrometría, Spécification, Specification, Especificación, Système sur puce, System on a chip, Sistema sobre pastilla, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Lucent Technologies Network Systems GmbH
University of Erlangen-Nuremberg, Germany
University of Erlangen-Nuremberg, Germany
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16075753
Database:
PASCAL Archive
Weitere Informationen
This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or being developed for a multisite ASIC design project from the first specification up to the gate level netlist: our multi-site data management environment VHDLDevSys, our multi-use and re-use library ADK-Lib and our multi-platform VHDL/C++ simulation/verification environment PROVerify together with the employment of formal methods.