Treffer: Embedded context aware hardware component generation for dataflow system exploration

Title:
Embedded context aware hardware component generation for dataflow system exploration
Authors:
MCALLISTER, John, WOODS, Roger, WALKE, Richard
Source:
Computer systems : architectures, modeling, and simulation (Samos, 21-23 July 2003 & 19-21 July 2004)Lecture notes in computer science. :254-263
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture circuit, Circuit architecture, Arquitectura circuito, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Calculateur embarqué, Boarded computer, Calculador embarque, Contexte, Context, Contexto, Flot donnée, Data flow, Flujo datos, Personnalisation, Customization, Personalización, Propriété intellectuelle, Intellectual property, Propiedad intelectual, Signal complexe, Complex signal, Señal compleja, Signal numérique, Digital signal, Señal numérica, Traitement numérique, Digital processing, Tratamiento digital, Traitement signal, Signal processing, Procesamiento señal, Sensibilité contexte, Context aware, Sensibilidad contexto
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Institute for Electronic, Communication and Information Technology (ECIT), Queens University Belfast, Belfast, BT9 5AH, United Kingdom
Real Time Embedded Systems (RTES), QinetiQ Ltd., St. Andrew's Road, Great Malvern, Worcestershire WR14 3PS, United Kingdom
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16075761
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16075761
Database:
PASCAL Archive

Weitere Informationen

Techniques for the rapid deployment and architectural exploration of complex digital signal processing algorithms on embedded processor platforms are gaining popularity. These become significantly more complicated when dedicated hardware components need to be integrated. The models on which such design methodologies and tools are based highlight the system level inflexibility with both pre-designed intellectual property cores and most customized component creation techniques. This paper presents a technique for overcoming these deficiencies using a dataflow model of computation, by allowing flexible circuit architectures to be created that can be optimized as desired, providing increased throughput with no extra resource usage in some situations.