Result: Design and implementation of a CFAR processor for target detection
Title:
Design and implementation of a CFAR processor for target detection
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :943-947
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 5 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Algorithme adaptatif, Adaptive algorithm, Algoritmo adaptativo, Architecture circuit, Circuit architecture, Arquitectura circuito, Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Détection cible, Target detection, Detección blanco, Méthode adaptative, Adaptive method, Método adaptativo, Méthode minimax, Minimax method, Método minimax, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Réseau porte programmable, Field programmable gate array, Red puerta programable, Signal numérique, Digital signal, Señal numérica, Taux fausse alarme, False alarm rate, Porcentaje falsa alarma, Temps réel, Real time, Tiempo real, Traitement numérique, Digital processing, Tratamiento digital, Traitement parallèle, Parallel processing, Tratamiento paralelo, Traitement pipeline, Pipeline processing, Traitement signal, Signal processing, Procesamiento señal
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Computer Science Department, INAOE, Apdo. Postal 51 & 216, Tonantzintla, Puebla, Mexico
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107481
Database:
PASCAL Archive
Further Information
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.