• Simulation platform for archit...

Result: Simulation platform for architectural verification and performance analysis in core-based SoC design

Title:
Simulation platform for architectural verification and performance analysis in core-based SoC design
Authors:
BIDARTE, Unai, ASTARLOA, Armando, MARTIN, José Luis, ANDREU, Jon
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :965-969
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 13 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Analyse statistique, Statistical analysis, Análisis estadístico, Approche probabiliste, Probabilistic approach, Enfoque probabilista, Architecture circuit, Circuit architecture, Arquitectura circuito, Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Evaluation performance, Performance evaluation, Evaluación prestación, Interface graphique, Graphical interface, Interfaz grafica, Interface utilisateur, User interface, Interfase usuario, Réseau porte programmable, Field programmable gate array, Red puerta programable, Réutilisation, Reuse, Reutilización, Synthèse commande, Control synthesis, Síntesis control, Système sur puce, System on a chip, Sistema sobre pastilla, Transmission donnée, Data transmission, Transmisión datos
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
University of the Basque Country, E.T.S. de Ingeniería de Bilbao, Urquijo s/n, 48013 Bilbao, Spain
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107483
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107483
Database:
PASCAL Archive

Further Information

In complex SoC designs verification consumes more than half of the overall design effort. Design reuse is a critical element in closing the SoC design gap, but it is not enough. A generic core-based architecture for circuits that require high volume data transfer control was designed. After some experience in reusing the architecture, a key improvement has recently been undertaken: a reusable simulation platform. The complexity of architectural verification and performance analysis has been greatly alleviated by means of a monitor module that processes all the events on the SoC and an Architecture Specific Graphical User Interface (ASGUI) that shows all the data transfers while simulation is running. The generation of bitrate and latency statistics is fully automated.