Treffer: Minimum sum of absolute differences implementation in a single FPGA device
Title:
Minimum sum of absolute differences implementation in a single FPGA device
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :986-990
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 5 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Arithmétique, Arithmetics, Aritmética, Conception circuit, Circuit design, Diseño circuito, Estimation mouvement, Motion estimation, Estimación movimiento, Mesure déplacement, Displacement measurement, Medición desplazamiento, Réseau porte programmable, Field programmable gate array, Red puerta programable, Troncature, Truncation, Truncamiento
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. of Electrotechnics and Electronics, University of Córdoba, Spain
Dept. of Computer Architecture, University of Málaga, Spain
Dept. of Computer Architecture, University of Málaga, Spain
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107485
Database:
PASCAL Archive
Weitere Informationen
Most of Block based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is proposed. Thanks to the use of the on-line arithmetic (OLA) two goal are achieved: it is possible to implement a full 16 x 16 macroblock SAD in a single FPGA device and it permits us to speed up the computation by early truncation of the SAD calculation. Reconfigurable devices allows us to change 8 x 8 or 16 x 16 pixels per block models. Comparison with other related works are provided.