Treffer: Implementation of Elliptic Curve Cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer
Title:
Implementation of Elliptic Curve Cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer
Authors:
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :1001-1005
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 5 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Architecture système, System architecture, Arquitectura sistema, Calculateur hybride, Hybrid computer, Computadora híbrida, Conception circuit, Circuit design, Diseño circuito, Courbe elliptique, Elliptic curve, Curva eliptica, Cryptographie clé publique, Public key cryptography, Langage description matériel informatique, Hardware description languages, Microprocesseur, Microprocessor, Microprocesador, Porte logique, Logic gate, Puerta lógica, Protocole internet, Internet protocol, Protocolo internet, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système hybride, Hybrid system, Sistema híbrido, Temps exécution, Execution time, Tiempo ejecución
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
ECE Department, George Mason University, 4400 University Drive, Fairfax, VA 22030, United States
ECE Department, The George Washington University, 801 22nd Street NW, Washington, D.C., United States
ECE Department, The George Washington University, 801 22nd Street NW, Washington, D.C., United States
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107486
Database:
PASCAL Archive
Weitere Informationen
Reconfigurable Computers are general-purpose high-end computers based on a hybrid architecture and close system-level integration of traditional microprocessors and Field Programmable Gate Arrays (FPGAs). In this paper, we present an application of reconfigurable computers to developing a low-latency implementation of Elliptic Curve Cryptosystems, an emerging class of public key cryptosystems used in secure Internet protocols, such as IPSec. An issue of partitioning the description between C and VHDL, and the associated trade-offs are studied in detail. End-to-end speed-ups in the range of 895 to 1300 compared to the pure microprocessor execution time are demonstrated.