Treffer: The implementation of a FPGA hardware Debugger system with minimal system overhead

Title:
The implementation of a FPGA hardware Debugger system with minimal system overhead
Authors:
TOMBS, J, AGUIRRE ECHANOVE, M. A, MUNOZ, F, BAENA, V, TORRALBA, A, FERNANDEZ-LEON, A, TORTOSA, F
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :1062-1066
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 6 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Débogage, Debugging, Puesta a punto programa, Elément architectural, Design feature, Elemento arquitectural, Emulateur, Emulator, Emulador, Prototypage rapide, Rapid prototyping, Prototipificación rápida, Réseau porte programmable, Field programmable gate array, Red puerta programable, Synthèse commande, Control synthesis, Síntesis control, Système conversationnel, Interactive system, Sistema interactivo, Temps réel, Real time, Tiempo real
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Escuela de Ingenieros, University of Seville, Camino de los descubrimientos s/n, Spain
ESA/ESTEC Noordwijk ZH, Netherlands
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107496
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107496
Database:
PASCAL Archive

Weitere Informationen

FPGAs provide powerful hardware emulation platforms for rapid prototyping of digital designs. This potential is usually restricted to overall system level emulation, with interactive debugging possibilities limited to the real-time observation of external signals. This article describes the most recent advances made in the UNSHADES[1] system, where unlike most commercial packages, signals need not be previously selected, nor are limited in number or size by the internal memory available. This system, which adds a small debug controller to the design to be inspected, provides many new design debugging features such as single stepping, state modification or register inspection over the entire design. The debug controller provides these powerful debugging operations without the need for large design modification whilst occupying itself very little FPGA resources. A minimal debug controller implemented in a virtex-II FPGA requires the occupation of just 3 IO pins and 43 logic slices; over half of these logic slices are dedicated to an optional 32-bit cycle counter.