Result: Monte Carlo radiative heat transfer simulation on a reconfigurable computer

Title:
Monte Carlo radiative heat transfer simulation on a reconfigurable computer
Authors:
GOKHALE, Maya, FRIGO, Janette, AHRENS, Christine, TRIPP, Justin L, MINNICH, Ron
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :95-104
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 15 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Microprocesseur, Microprocessor, Microprocesador, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Processeur pipeline, Pipeline processor, Procesador oleoducto, Réseau porte programmable, Field programmable gate array, Red puerta programable, Simulation ordinateur, Computer simulation, Simulación computadora, Superordinateur, Supercomputer, Supercomputador, Transfert chaleur, Heat transfer, Transferencia térmica, Transfert radiatif, Radiative transfer, Transferencia radiativa, Type donnée, Data type, Tipo dato, Unité arithmétique, Arithmetic unit, Unidad aritmética, Virgule flottante, Floating point, Coma flotante
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Los Alamos National Laboratory, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107514
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107514
Database:
PASCAL Archive

Further Information

Recently, the appearance of very large (3 - 10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet relatively little experience with mapping an application-specific floating point loop onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and Virtex II Pro FPGAs and compare performance with three Pentium IV Xeon microprocessors. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speed up of 10.37×. We analyze the trade-offs between hardware and software to characterize the algorithms that will perform well on current and future FPGA architectures.