Result: Solving SAT with a context-switching virtual clause pipeline and an FPGA embedded processor
Title:
Solving SAT with a context-switching virtual clause pipeline and an FPGA embedded processor
Authors:
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :344-353
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 23 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Algorithmique, Algorithmics, Algorítmica, Architecture reconfigurable, Reconfigurable architectures, Calculateur embarqué, Boarded computer, Calculador embarque, Conception circuit, Circuit design, Diseño circuito, Couplage, Coupling, Acoplamiento, Extensibilité, Scalability, Estensibilidad, Logique propositionnelle, Propositional logic, Lógica proposicional, Processeur pipeline, Pipeline processor, Procesador oleoducto, Réseau porte programmable, Field programmable gate array, Red puerta programable, Satisfaction contrainte, Constraint satisfaction, Satisfaccion restricción
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
INESC-ID/IST-Technical University of Lisbon/Coreworks, Lda R. Alves Redol, 9, 1000-029 Lisboa, Portugal
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107523
Database:
PASCAL Archive
Further Information
This paper proposes an architecture that combines a context-switching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling between configware and software. The virtual circuit is an arbitrarily large clause pipeline, partitioned into sections of a number of stages (hardware pages), which can fit in the configware. The hardware performs logical implications, grades and select decision variables. The software monitors the data and takes care of the high-level algorithmic flow. Experimental results show speed-ups that reach up to two orders of magnitude in one case. Future improvements for addressing scalability and performance issues are also discussed.