Treffer: Network-on-chip for reconfigurable systems: From high-level design down to implementation

Title:
Network-on-chip for reconfigurable systems: From high-level design down to implementation
Authors:
BARTIC, T. A, DESMET, D, MIGNOLET, J-Y, MARESCAUX, T, VERKEST, D, VERNALDE, S, LAUWEREINS, R, MILLER, J, ROBERT, F
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :637-647
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 15 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Circuit décodeur, Decoding circuit, Circuito desciframiento, Conception circuit, Circuit design, Diseño circuito, Evaluation performance, Performance evaluation, Evaluación prestación, Langage description matériel informatique, Hardware description languages, Optimisation, Optimization, Optimización, Réseau communication, Communication network, Red de comunicación, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système sur puce, System on a chip, Sistema sobre pastilla
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Université Libre de Bruxelles, Belgium
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107538
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107538
Database:
PASCAL Archive

Weitere Informationen

In order to use Networks-on-Chip as communication infrastructure for heterogeneous, reconfigurable Systems-on-Chip, a set of tools are needed that would allow for an evaluation of the performance of a particular network, and a fast implementation of the system. In this paper we present two models that can be used in the design and implementation of the platform and of its applications. The first model is written in synthesisable VHDL, and it is highly parameterizable allowing a fast network implementation. The second one is a cycle-accurate SystemC model that allows a fast exploration of the design space. The models offer complementary information and help the platform and the application designers to make the best trade-offs. We present how the two models can be used for platform optimization and implementation and for application mapping, using a motion JPEG decoder as a case study. We analyze the system performance as a function of the different design parameters and we present the implementation results for the reconfigurable platform that we have built.