Treffer: Increasing pipelined IP core utilization in process networks using exploration

Title:
Increasing pipelined IP core utilization in process networks using exploration
Authors:
ZISSULESCU, Claudiu, KIENHUIS, Bart, DEPRETTERE, Ed
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :690-699
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Chemin données, Data path, Camino datos, Conception circuit, Circuit design, Diseño circuito, Processeur pipeline, Pipeline processor, Procesador oleoducto, Protocole internet, Internet protocol, Protocolo internet, Réseau porte programmable, Field programmable gate array, Red puerta programable
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107541
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107541
Database:
PASCAL Archive

Weitere Informationen

At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platforms, such as FPGAs, using IP cores to implement the data-path of the applications. A particular characteristic of the derived networks is the existence of selfloops. These selfloops have a large impact on the utilization of IP cores in the final hardware implementation of a Process Network (PN), especially if the IP cores are deeply pipelined. In this paper, we present an exploration methodology that uses feedback provided by the Laura tool to increase the utilization of IP cores embedded in our PN. Using this exploration, we go from 60MFlops to 1,7GFlops for the QR algorithm using the same number of resources except for memory.