Treffer: SOC and RTOS: Managing IPS and tasks communications
Title:
SOC and RTOS: Managing IPS and tasks communications
Authors:
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :710-718
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 7 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Encapsulation, Encapsulación, Extraction information, Information extraction, Extracción información, Gestion transmission, Communications managing, Gestión transmisión, Partage ressource, Resource sharing, Partición recursos, Protocole internet, Internet protocol, Protocolo internet, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système exploitation, Operating system, Sistema operativo, Système sur puce, System on a chip, Sistema sobre pastilla, Enveloppeur, Wrapper, Envolvero
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
ETIS Laboratory, UMR CNRS 8051, ENSEA - Université de Cergy-Pontoise, 6 av. du Ponceau, 95014 Cergy-Pontoise, France
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107543
Database:
PASCAL Archive
Weitere Informationen
We present in this paper a development method for SOC platforms associating a processor running a RTOS and hardware IP's. This method is based on encapsulating IP's for unifying communications and resource sharing between software and hardware tasks. A hardware wrapper that abstracts the IP behaviours through a standard interface and a software encapsulation (the IP Alter Ego) thereby giving access to the Operating System functions are presented. Details about implementing this model on two different FPGA platforms are given.