Treffer: Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures

Title:
Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures
Authors:
BANSAL, Nikhil, GUPTA, Sumit, DUTT, Nikil, NICOLAU, Alex, GUPTA, Rajesh
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :891-899
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 20 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Borne inférieure, Lower bound, Cota inferior, Conception circuit, Circuit design, Diseño circuito, Equation parabolique, Parabolic equation, Ecuación parabólica, Fonction coût, Cost function, Función coste, Ordonnancement, Scheduling, Reglamento, Priorité, Priority, Prioridad, Retard, Delay, Retraso, Réseau porte programmable, Field programmable gate array, Red puerta programable, Structure gros grain, Coarse grain structure, Estructura grano grueso, Transmission donnée, Data transmission, Transmisión datos
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
University of California, Irvine, United States
Tallwood Venture Capital, Palo Alto, United States
University of California, San Diego, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107552
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107552
Database:
PASCAL Archive

Weitere Informationen

Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.