Result: The impact of pipelining on energy per operation in field-programmable gate arrays
Title:
The impact of pipelining on energy per operation in field-programmable gate arrays
Authors:
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :719-728
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 22 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Analyse amas, Cluster analysis, Analisis cluster, Architecture reconfigurable, Reconfigurable architectures, Classification, Clasificación, Conception circuit, Circuit design, Diseño circuito, Consommation énergie, Energy consumption, Consumo energía, Densité élevée, High density, Densidad elevada, Grande vitesse, High speed, Gran velocidad, Processeur pipeline, Pipeline processor, Procesador oleoducto, Réseau porte programmable, Field programmable gate array, Red puerta programable, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. of Electrical and Computer Eng., University of British Columbia, Vancouver, B.C., Canada
Department of Computing, Imperial College, London, United Kingdom
Department of Computing, Imperial College, London, United Kingdom
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107567
Database:
PASCAL Archive
Further Information
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.