Result: FPGA implementation of a novel all digital PLL architecture for PCR related measurements in DVB-T

Title:
FPGA implementation of a novel all digital PLL architecture for PCR related measurements in DVB-T
Authors:
MANNINO, Christian, RABAH, Hassan, TANOUGAST, Camel, BERVILLER, Yves, JANIAUT, Michael, WEBER, Serge
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :1027-1031
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 7 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Boucle verrouillage phase, Phase locked loop, Bucle enclavamiento fase, Calculateur embarqué, Boarded computer, Calculador embarque, Circuit décodeur, Decoding circuit, Circuito desciframiento, Circuit numérique, Digital circuit, Circuito numérico, Conception circuit, Circuit design, Diseño circuito, Défaut, Defect, Defecto, Filtre, Filter, Filtro, Gigue, Jitter, Fluctuación, Qualité service, Service quality, Calidad servicio, Réseau porte programmable, Field programmable gate array, Red puerta programable, Signal vidéo, Video signal, Señal video
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
U.H.P., Faculté des Sciences, Laboratoire d'Instrumentation Electronique de Nancy, BP239, 54500 Vandoeuvre-les-Nancy, France
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107576
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107576
Database:
PASCAL Archive

Further Information

The MPEG-2 DVB Transport Stream domain carries in addition to audio and video data a Program Clock Reference(PCR). This PCR is used to synchronize the MPEG-2 decoder clock on the receiver side for a given program. The PCR values can be affected by an offset inaccuracy due to encoder imperfection or by the network jitter. The measurement of different PCR parameters like drift, precision and jitter are necessary for evaluating the decodability efficiency. These measurements are generally achieved using a Phase Lock Loop and a set of measurement filters as it is recommended in the DVB-T QoS measurement standard. In this paper, we propose a FPGA implementation of an all digital PLL and its associated measurement filters. We demonstrate how it is possible to process all available programs in a DVB-T transport stream by using an FPGA with an associated embedded processor.