• Area*time optimized hogenauer...

Treffer: Area*time optimized hogenauer channelizer design using FPL devices

Title:
Area*time optimized hogenauer channelizer design using FPL devices
Authors:
MEYER-BÄSE, Uwe, RAO, Suhasini, RAMIREZ, Javier, GARCIA, Antonio
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :384-393
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 10 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Additionneur, Adder, Adicionador, Architecture reconfigurable, Reconfigurable architectures, Arithmétique, Arithmetics, Aritmética, Circuit programmable, Programmable circuit, Circuito programable, Conception circuit, Circuit design, Diseño circuito, Densité, Density, Densidad, Dispositif logique programmable, Programmable logic devices, Microprocesseur, Microprocessor, Microprocesador, Prototypage rapide, Rapid prototyping, Prototipificación rápida, Réseau porte programmable, Field programmable gate array, Red puerta programable, Signal numérique, Digital signal, Señal numérica, Technologie communication, Communication technology, Tecnología comunicacíon, Traitement numérique, Digital processing, Tratamiento digital, Traitement signal, Signal processing, Procesamiento señal
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical and Computer Engineering, FAMU-FSU College of Engineering, Florida State University, United States
Department of Electronics and Computer Technology University of Granada, Spain
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107582
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107582
Database:
PASCAL Archive

Weitere Informationen

Field-programmable logic devices (FPLDs) are on the verge of revolutionizing the digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPLDs were considered to be only a rapid prototyping and low-volume production technology. FPLDs are now attempting to move into the mainstream DSP as their density and performance envelope have steadily improved. While evidence now supports the claim that FPLDs can accelerate selected low-end DSP applications, the technology remains limited in its ability to realize high-end DSP solutions. This is primarily due to systemic weaknesses in FPLD-facilitated arithmetic processing. It will be shown that in such cases, a modified carry save adder (MCSA) arithmetic can become an enabling technology for realizing embedded high-end FPLD-centric DSP solutions. This thesis is developed in the context of a demonstrated MCSA/FPLD synergy and the application of the new technology to communication signal processing. Design synthesis results for Xilinx and Altera FPLDs are provided and show 22-164% speed improvement compared to 2C designs and require lower costs (A*T) in most study cases.