Treffer: Efficient modular division implementation: ECC over GF(p) affine coordinates application

Title:
Efficient modular division implementation: ECC over GF(p) affine coordinates application
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :231-240
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 11 ref
Original Material:
INIST-CNRS
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Université Catholique de Louvain, UCL Crypto Group, Laboratoire de Microélectronique (DICE), Place du Levant 3, 1348 Louvain-La-Neuve, Belgium
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107589
Database:
PASCAL Archive

Weitere Informationen

Elliptic Curve Public Key Cryptosystems (ECPKC) are becoming increasingly popular for use in mobile appliances where bandwidth and chip area are strongly constrained. For the same level of security, ECPKC use much smaller key length than the commonly used RSA. The underlying operation of affine coordinates elliptic curve point multiplication requires modular multiplication, division/inversion and addition/substraction. To avoid the critical division/inversion operation, other coordinate systems may be chosen, but this implies more operations and a strong increase in memory requirements. So, in area and memory constrained devices, affine coordinates should be preferred, especially over GF(p). This paper presents a powerful reconfigurable hardware implementation of the Takagi modular divider algorithm. Resulting 256-bit circuits achieved a ratio throughput/area improved by at least 900 % of the only known design in Xilinx Virtex-E technology. Comparison with typical modular multiplication performance is carried out to suggest the use of affine coordinates also for speed reason.