Treffer: Compact buffered routing architecture

Title:
Compact buffered routing architecture
Authors:
LODI, A, GIANSANTE, R, CHIESA, C, CICCARELLI, L, CAMPI, F, TOMA, M
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :179-188
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 10 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Chemin critique, Critical path, Recorrido crítico, Conception circuit, Circuit design, Diseño circuito, Contexte, Context, Contexto, Décodage, Decoding, Desciframiento, Retard, Delay, Retraso, Routage, Routing, Enrutamiento, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système tampon, Buffer system, Sistema amortiguador, Topologie, Topology, Topología
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
ARCES University of Bologna, Viale Pepoli 3/2, 40123 Bologna, Italy
STMicroelectronics, NVM-DP, CR&D, Agrate Brianza, Italy
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107599
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107599
Database:
PASCAL Archive

Weitere Informationen

In this paper we propose a new routing architecture, based on a new switch called T-switch, which we implement in two different versions. Our approach is based on a modified disjoint topology in order to reduce the number of buffers required and on the introduction of a decoding stage between configuration memories and the switch to reduce the number of SRAM cells. This solution is particularly suitable for multi-context arrays, where configuration memory cells need to be replicated as many times as the number of contexts. The buffered switch proposed has been implemented in two different gate array architectures, in order to evaluate its effectiveness. The results show that the T-switch routing architecture reduces the device area occupation up to 29% in a 4-context array. We also show that the critical path delay is reduced, while routability is substantially unaffected.