Treffer: A system level resource estimation tool for FPGAs

Title:
A system level resource estimation tool for FPGAs
Authors:
CHANGCHUN SHI, HWANG, James, MCMILLAN, Scott, ROOT, Ann, SINGH, Vinay
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :424-433
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 9 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Code temps, Time code, Código tiempo, Compilation, Compilación, Conception circuit, Circuit design, Diseño circuito, Haute performance, High performance, Alto rendimiento, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système asservi, Feedback system, Servomecanismo
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, United States
Xilinx Inc., 2100 Logic Drive, San Jose, CA, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107614
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107614
Database:
PASCAL Archive

Weitere Informationen

High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required provides the system designer important feedback on area and cost, which is valuable even during early design iterations. Previous approaches to hardware resource estimation suffer a combination of inaccuracy, slowness, and/or high complexity, which limits their practicality at the algorithm definition stage. We address these restrictions with a fast resource estimation tool incorporated in the Xilinx System Generator. Implemented using MATLAB code, the estimator run time is proportional to the Simulink compilation time, and typically takes from seconds to minutes depending upon the size of the Simulink model. Estimates are conservative, and accurate to within 10% of the post-mapping implementation report. In this paper, we explain how block resource information is characterized in a MATLAB function. This characterization also estimates logic that will be trimmed during synthesis and mapping. Finally, we describe how these estimation functions are integrated within Simulink in a user-friendly and automated infrastructure. This approach has been incorporated in System Generator since version 3.1.