Result: Memory-model-sensitive data race analysis

Title:
Memory-model-sensitive data race analysis
Authors:
YUE YANG, GOPALAKRISHNAN, Ganesh, LINDSTROM, Gary
Source:
Formal methods and software engineering (Seattle WA, 8-12 November 2004)Lecture notes in computer science. :30-45
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 36 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Génie logiciel, Software engineering, Analyse programme, Program analysis, Análisis programa, Capteur mesure, Measurement sensor, Captador medida, Documentation, Documentación, Développement logiciel, Software development, Desarrollo logicial, Exactitude programme, Program correctness, Exactitud programa, Extensibilité, Scalability, Estensibilidad, Langage JAVA, JAVA language, Lenguaje JAVA, Langue source, Source language, Lengua fuente, Modèle donnée, Data models, Modélisation, Modeling, Modelización, Multitâche, Multithread, Multitarea, Méthode formelle, Formal method, Método formal, Programmation logique avec contrainte, Constraint logic programming, Programación lógica con restricción, Résolution problème, Problem solving, Resolución problema, Satisfaction contrainte, Constraint satisfaction, Satisfaccion restricción, Sémantique formelle, Formal semantics, Semántica formal, Vérification programme, Program verification, Verificación programa, Accès concurrent, Race, Acceso simultáneo
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Microsoft Research, One Microsoft Way, Redmond WA, 98052, United States
School of Computing, University of Utah, Salt Lake City, UT, 84112, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16334774
Rights:
Copyright 2005 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.16334774
Database:
PASCAL Archive

Further Information

We present a memory-model-sensitive approach to validating correctness properties for multithreaded programs. Our key insight is that by specifying both the inter-thread memory consistency model and the intra-thread program semantics as constraints, a program verification task can be reduced to an equivalent constraint solving problem, thus allowing an exhaustive examination of all thread interleavings precisely allowed by a given memory model. To demonstrate, this paper formalizes race conditions according to the new Java memory model, for a simplified but non-trivial source language. We then describe the implementation of a memory-model-sensitive race detector using constraint logic programming (CLP). In comparison with conventional program analysis, our approach does not offer the same kind of performance and scalability due to the complexity involved in exact formal reasoning. However, we show that a formal semantics can serve more than documentation purposes - it can be applied as a sound basis for rigorous property checking, upon which more scalable methods can be derived.