Treffer: High-efficient architectures of the context adaptive binary arithmetic coder for H.264/AVC
Title:
High-efficient architectures of the context adaptive binary arithmetic coder for H.264/AVC
Authors:
Source:
IWSSIP'04 : international workshop on systems, signals and image processing (Poznan, 13-15 September 2004). :167-170
Publisher Information:
Poznan: PTETIS, 2004.
Publication Year:
2004
Physical Description:
print, 5 ref
Original Material:
INIST-CNRS
Subject Terms:
Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Telecommunications et theorie de l'information, Telecommunications and information theory, Théorie de l'information, du signal et des communications, Information, signal and communications theory, Théorie du signal et des communications, Signal and communications theory, Codage, codes, Coding, codes, Télécommunications, Telecommunications, Systèmes, réseaux et services de télécommunications, Systems, networks and services of telecommunications, Transmission et modulation (techniques et équipements), Transmission and modulation (techniques and equipments), Radiodiffusion. Vidéocommunications. Audiovisuel, Broadcasting. Videocommunications. Audiovisual, Télévision, Television, Codage adaptatif, Adaptive coding, Codificación adaptativa, Codage binaire, Binary coding, Codificación binaria, Code arithmétique, Arithmetic code, Código aritmético, Débit information, Information rate, Índice información, Horloge, Clock, Reloj, Implémentation, Implementation, Implementación, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système NTSC, NTSC-system, Sistema NTSC, Temps réel, Real time, Tiempo real, Transmission information, Information transmission, Transmisión información, Télévision haute résolution, High definition television, Televisión alta definición
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Warsaw University of Technology, Institute of Radioelectronics, Nowowiejska 15/19, 00-665 Warszawa, Poland
Rights:
Copyright 2005 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Telecommunications and information theory
Accession Number:
edscal.16744585
Database:
PASCAL Archive
Weitere Informationen
This paper presents architecture design of the context adaptive binary arithmetic coding (CABAC) in H.264/AVC. The pipelined architecture has been implemented in two variants targeting Altera FPGA Stratix devices. The first one process one symbol per clock cycle at the working frequency of 140 MHz. The second accepts two symbols per clock cycle at the frequency of 100 MHz. Evaluation results show that the engines meets throughput requirements of real-time television systems such as: PAL, NTSC, and even HDTV.