Treffer: Demonstration of the multi-bit sigma-delta A/D converter with the decimation filter

Title:
Demonstration of the multi-bit sigma-delta A/D converter with the decimation filter
Authors:
SEKIYA, A, OKADA, K, NISHIDO, Y, FUJIMAKI, A, HAYAKAWA, H
Source:
The 2004 Applied Superconductivity Conference, Jacksonville, FL, USA, October 3-8, 2004IEEE transactions on applied superconductivity. 15(2):340-343
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2005.
Publication Year:
2005
Physical Description:
print, 14 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Oscillateurs, résonateurs, synthétiseurs, Oscillators, resonators, synthetizers, Convertisseurs de signal, Signal convertors, Circuits numériques, Digital circuits, Bistable, Biestable, Circuit intégré supraconducteur, Superconducting integrated circuits, Convertisseur AN, AD converter, Convertidor AN, Convertisseur NA, DA converter, Convertidor NA, Echantillonnage, Sampling, Muestreo, Echantillonneur, Sampler, Muestreador, Fréquence échantillonnage, Sampling frequency, Frecuencia muestreo, Horloge, Clock, Reloj, Logiciel MATLAB, MATLAB software, Programa MATLAB, Modulateur, Modulator, Modulador, Modulation sigma delta, Sigma-delta modulation, Ordre 2, Second order, Orden 2, Oscillateur anneau, Ring oscillator, Oscilador anillo, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Signal analogique, Analog signal, Señal analógica, Signal modulé, Modulated signal, Señal modulada, Simulateur, Simulator, Simulador, Temps retard, Delay time, Tiempo retardo, Plage dynamique sans parasite, Spurious free dynamic range, Analog-to-digital converter, decimation filter, sigma-delta modulator, single-flux-quantum
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Information Electronics, Nagoya University, Nagoya 464-8603, Japan
Department of Quantum Engineering, Nagoya University, Nagoya 464-8603, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16926394
Rights:
Copyright 2005 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.16926394
Database:
PASCAL Archive

Weitere Informationen

We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.