Treffer: New radix-2 to the 4th power pipeline FFT processor

Title:
New radix-2 to the 4th power pipeline FFT processor
Source:
IEICE transactions on electronics. 88(8):1740-1746
Publisher Information:
Oxford: Oxford University Press, 2005.
Publication Year:
2005
Physical Description:
print, 10 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Circuit intégré, Integrated circuit, Circuito integrado, Evaluation performance, Performance evaluation, Evaluación prestación, Multiplexage fréquence orthogonal, Orthogonal frequency division multiplexing, Multiplaje frecuencia ortogonal, Multiplicateur, Multiplier, Multiplicador, Performance algorithme, Algorithm performance, Resultado algoritmo, Processeur pipeline, Pipeline processor, Procesador oleoducto, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Transformation Fourier rapide, Fast Fourier transformation, Transformación Fourier rápida, CSD, FFT, SDF, multiplier, pipeline, radix
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Division of Electronics and Information Engineering, Chonbuk National University, Korea, Republic of
ISSN:
0916-8524
Rights:
Copyright 2005 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.17006379
Database:
PASCAL Archive

Weitere Informationen

This paper proposes a new modified radix-24 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35μm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.