• Low power multi-segment sequen...

Treffer: Low power multi-segment sequential one hot addressing architecture

Title:
Low power multi-segment sequential one hot addressing architecture
Authors:
TAN, K.-C. B, ARSLAN, T
Source:
IEE proceedings. Circuits, devices and systems. 153(2):159-166
Publisher Information:
Stevenage: Institution of Electrical Engineers, 2006.
Publication Year:
2006
Physical Description:
print, 7 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Adressage, Addressing, Direccionamiento, Architecture circuit, Circuit architecture, Arquitectura circuito, Conception circuit, Circuit design, Diseño circuito, Processeur signal numérique, Digital signal processor, Procesador señal numérica, Puissance faible, Low power, Potencia débil, Traitement sériel, Serial processing, Procesamiento serial
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Fujitsu Microelectronics Asia Pte Ltd., 151 Lorong Chuan, New Tech Park, 05-08, Singapore 556741, Singapore
Institute of Integrated Micro and Nano Systems, School of Engineering and Electronics, The University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, Scotland, United Kingdom
ISSN:
1350-2409
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=17733154
Rights:
Copyright 2006 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.17733154
Database:
PASCAL Archive

Weitere Informationen

Sequential addressing is one of the essential power-consuming parts of digital signal processing (DSP), which is mainly used for sequential memory and coefficient selection. The use of sequential addressing is not only widespread, but also particularly important in a wide variety of DSP applications as most of the computation process proceeds in a sequential manner. Therefore, by reducing both the power of the sequential memory addressing hardware and accesses within the DSP system, the overall power consumption of the system will be effectively reduced. A novel scalable low power multi-segment one-hot all-sequential addressing architecture (MSML-OHA) is presented. This architecture, implemented in 0.18 μm CMOS technology, reduces power dissipation by more than 20% compared to conventional counter-decoder architecture.