Treffer: Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
Title:
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
Source:
ICCAD-2005 (International Conference on Computer Aided Design). :238-245
Publisher Information:
New York NY; Piscataway NJ: ACM, IEEE, 2005.
Publication Year:
2005
Physical Description:
print, 24 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Algorithme adaptatif, Adaptive algorithm, Algoritmo adaptativo, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Architecture parallèle, Parallel architectures, Architecture réseau, Network architecture, Arquitectura red, Architecture système, System architecture, Arquitectura sistema, Circuit intégré, Integrated circuit, Circuito integrado, Coeur propriété intellectuelle, Intellectual property core, Núcleo propiedad intelectual, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Diseño circuito, Densité élevée, High density, Densidad elevada, Défaillance, Failures, Fallo, Implantation circuit intégré, Integrated circuit layout, Interblocage, Deadlock, Interbloqueo, Ordinateur parallèle, Parallel computer, Ordenador paralelo, Réseau interconnexion, Interconnection network, Red interconexión, Réseau maillé, Meshed network, Red mallada cerrada, Système sur puce, System on a chip, Sistema sobre pastilla, Traitement parallèle, Parallel processing, Tratamiento paralelo
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Institute of Microelectronic Systems, Darmstadt University of Technology, Germany
Rights:
Copyright 2006 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.17834144
Database:
PASCAL Archive
Weitere Informationen
Routing is one of the most crucial key factors which will decide over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-Mesh based Network-on-Chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.