• Solder joints layout design an...

Treffer: Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

Title:
Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology
Authors:
LEE, Chang-Chun, LEE, Chien-Chen, KU, Hsiao-Tung, CHANG, Shu-Ming, CHIANG, Kuo-Ning
Source:
Microelectronics and reliability. 47(2-3):196-204
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 14 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Dispositifs à transfert de charge, Charge transfer devices, Assemblage brasage tendre, Soldered joint, Junta soldada, Assemblage circuit intégré, Integrated circuit bonding, Brasage avec refusion, Reflow soldering, Soldeo con refusión, Circuit intégré, Integrated circuit, Circuito integrado, Composant électronique, Electronic component, Componente electrónico, Couche double, Double layers, Cycle thermique, Thermal cycle, Ciclo térmico, Dilatation thermique, Thermal expansion, Dilatación térmica, Dispositif CCD, Charge coupled device, Dispositivo carga acoplada, Durabilité, Durability, Durabilidad, Durée vie fatigue, Fatigue life, Longevidad fatiga, Défaillance, Failures, Fallo, Désadaptation, Mismatching, Desadaptación, Essai thermique, Thermal test, Prueba térmica, Fiabilité dispositif semiconducteur, Semiconductor device reliability, Imageur, Imager, Matrice formage, Die, Matriz formadora, Matériau composite, Composite material, Material compuesto, Miniaturisation, Miniaturization, Miniaturización, Mémoire accès direct dynamique, Dynamic random access memory, Mémoire accès direct, Random access memory, Memoria acceso directo, Packaging électronique, Electronic packaging, Packaging electrónico, Paramètre géométrique, Geometrical parameter, Parámetro geométrico, Pastille électronique, Wafer, Pastilla electrónica, Plan expérience, Experimental design, Plan experiencia, Résolution problème, Problem solving, Resolución problema, Surface réponse, Response surface, Superficie respuesta
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Advanced Microsystem Packaging and Nano-Mechanics Research Laboratory, Advanced Packaging Research Center, National Tsing Hua University and Electronics Research and Service Organization/ITRI, HsinChu 300, Tawain, Province of China
ISSN:
0026-2714
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18518713
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18518713
Database:
PASCAL Archive

Weitere Informationen

As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100 mm2 without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter.