• Thin film fully-depleted SOI f...

Treffer: Thin film fully-depleted SOI four-gate transistors

Title:
Thin film fully-depleted SOI four-gate transistors
Authors:
AKARVARDAR, K, CRISTOLOVEANU, S, BAWEDIN, M, GENTIL, P, BLALOCK, B. J, FLANDRE, D
Source:
EUROSOI'06 Conference. Selected papersSolid-state electronics. 51(2):278-284
Publisher Information:
Oxford: Elsevier Science, 2007.
Publication Year:
2007
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Couche appauvrissement, Depletion layer, Capa empobrecimiento, Couche mince, Thin film, Capa fina, Distribution potentiel, Potential distribution, Distribución potencial, Grille transistor, Transistor gate, Rejilla transistor, Méthode analytique, Analytical method, Método analítico, Seuil tension, Voltage threshold, Umbral tensión, Silicium, Silicon, Silicio, Technologie silicium sur isolant, Silicon on insulator technology, Tecnología silicio sobre aislante, Transconductance, Transconductancia, Transistor effet champ, Field effect transistor, Transistor efecto campo, Si, Coupling effects, Four-gate transistor, Fully-depleted SOI, Subthreshold swing, Threshold voltage
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Institut de Microélectronique, Electromagnétisme et Photonique (IMEP), INPG-Minatec 3 Parvis Louis Néel, 38016 Grenoble, France
Université Catholique de Louvain, Louvain-la-Neuve 1348, Belgium
ECE Department, The University of Tennessee, Knoxville, TN 37996, United States
ISSN:
0038-1101
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18658372
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18658372
Database:
PASCAL Archive

Weitere Informationen

The fully-depleted version of the SOI four-gate transistor (G4-FET) is introduced and its characteristics are systematically investigated. It is shown that the thinning-down of the silicon film promotes vertical coupling between the front and the back gates while mitigating the horizontal coupling between the lateral gates. As a consequence the direct influence of the lateral junction-gates on the body potential distribution is reduced. However, by biasing the back interface in inversion the junction-gates can indirectly modulate the body potential. This provides a very efficient control of the front-channel conduction parameters - such as threshold voltage, subthreshold swing and transconductance - by the junction-gates regardless the device width. The experimental results are clarified by 3-D device simulations and analytical modelling.