Treffer: The pipeline decomposition tree : An analysis tool for multiprocessor implementation of image processing applications

Title:
The pipeline decomposition tree : An analysis tool for multiprocessor implementation of image processing applications
Authors:
KO, Dong-Ik, BHATTACHARYYA, Shuvra S
Source:
CODES+ISSS 2006 (International Conference on Hardware/Software Codesign and System Synthesis). :52-57
Publisher Information:
New York NY: Association for Computing Machinery, 2006.
Publication Year:
2006
Physical Description:
print, 14 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Intelligence artificielle, Artificial intelligence, Reconnaissance des formes. Traitement numérique des images. Géométrie algorithmique, Pattern recognition. Digital image processing. Computational geometry, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Calculateur embarqué, Boarded computer, Calculador embarque, Conception circuit, Circuit design, Diseño circuito, Conception conjointe, Codesign, Diseño conjunto, Gestion tâche, Task scheduling, Gestión labor, Multiprocesseur, Multiprocessor, Multiprocesador, Ordonnancement, Scheduling, Reglamento, Parallélisme, Parallelism, Paralelismo, Personnalisation, Customization, Personalización, Processeur pipeline, Pipeline processor, Procesador oleoducto, Représentation système, System representation, Representación sistema, Structure donnée, Data structure, Estructura datos, Temps réel, Real time, Tiempo real, Traitement image, Image processing, Procesamiento imagen
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, 20742, United States
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18707328
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.18707328
Database:
PASCAL Archive

Weitere Informationen

Modem embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. This paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints.