Treffer: Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults

Title:
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults
Authors:
Source:
Selected best papers from ETS'06IET computers & digital techniques (Print). 1(3):246-255
Publisher Information:
Stevenage: Institution of Engineering and Technology, 2007.
Publication Year:
2007
Physical Description:
print, 36 ref
Original Material:
INIST-CNRS
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Advanced Reliable Systems (ARES) Laboratory, Department of Electrical Engineering, National Central University, Jhongli 320, Tawain, Province of China
ISSN:
1751-8601
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18789658
Database:
PASCAL Archive

Weitere Informationen

With shrinking transistor sizes and growing transistor density, testing neighbourhood pattern-sensitive faults (NPSFs) is increasingly important for semiconductor memories. A test methodology for detecting active NPSFs (ANPSFs) and static NPSFs (SNPSFs) in ternary content addressable memories (TCAMs) is presented. March-like and two-group test methods are two commonly used testing techniques for NPSFs in random access memories. Because of the special TCAM cell structure, however, using a unique test algorithm with only either a March-like or a two-group test operations are not time-efficient. A test methodology that employs both March-based and two-group testing to cover 100% ANPSFs and SNPSFs in TCAMs is proposed. The total test complexity of the proposed test methodology is 156 N for an N x K-bit TCAM. No TCAM circuit modification is needed to support the proposed test methodology.