Treffer: VSP: A gate stack analyzer
Title:
VSP: A gate stack analyzer
Authors:
Source:
14TH Workshop on dielectrics in microelectronics (WoDiM 2006)Microelectronics and reliability. 47(4-5):704-708
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 18 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs diélectriques et dispositifs à base de verre et de solides amorphes, Dielectric, amorphous and glass solid devices, Article synthèse, Review, Artículo síntesis, Condensateur MOS, MOS capacitor, Capacidad MOS, Courant fuite, Leakage current, Corriente escape, Effet quantique, Quantum effect, Efecto cuántico, Effet tunnel, Tunnel effect, Efecto túnel, Etat quasi lié, Quasi bound state, Estado cuasi ligado, Fiabilité, Reliability, Fiabilidad, Grille transistor, Transistor gate, Rejilla transistor, Inélasticité, Inelasticity, Inelasticidad, Multicouche, Multiple layer, Capa múltiple, Outil logiciel, Software tool, Herramienta software, Piégeage porteur charge, Charge carrier trapping, Captura portador carga
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Institut for Microelectronics, TU Wien Gusshausstr. 27-29, 1040 Wien, Austria
ISSN:
0026-2714
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18790367
Database:
PASCAL Archive
Weitere Informationen
An efficient software tool for investigations on novel stacked gate dielectrics with emphasis on reliability has been developed. The accumulation, depletion, and inversion of carriers in MOS capacitors is properly considered for n- and p-substrates. The effect of carrier quantization on the electrostatics and the leakage current is included by treating carriers in quasi-bound states (QBS) and continuum states. The effect of interface traps and bulk traps in arbitrarily stacked gate dielectrics is taken into account. Trap assisted tunneling (TAT) is incorporated assuming an inelastic single step tunneling process. A brief overview of implemented models is given. The capabilities of our tool are demonstrated by several examples.