Treffer: Verification of CDM circuit simulation using an ESD evaluation circuit
Title:
Verification of CDM circuit simulation using an ESD evaluation circuit
Authors:
Source:
Microelectronics and reliability. 47(7):1036-1043
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 13 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Analyse dommage, Failure analysis, Análisis avería, Circuit intégré, Integrated circuit, Circuito integrado, Conception circuit, Circuit design, Diseño circuito, Dispositif protection, Protective device, Dispositivo protección, Décharge électrostatique, Electrostatic discharge, Défaillance, Failures, Fallo, Optimisation, Optimization, Optimización, Packaging électronique, Electronic packaging, Packaging electrónico, Robustesse, Robustness, Robustez, Simulation circuit, Circuit simulation
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Freescale Semiconductor, Inc. 3501 Ed Bluestein Boulevard, MD: K10, Austin, TX 78721, United States
Robert Bosch GmbH, Tuebinger Strasse 123, 72703 Reutlingen, Germany
Integrated System Laboratory, Swiss Federal Institute of Technology (ETHZ), Gloriastrasse 35, 8092 Zurich, Switzerland
Robert Bosch GmbH, Tuebinger Strasse 123, 72703 Reutlingen, Germany
Integrated System Laboratory, Swiss Federal Institute of Technology (ETHZ), Gloriastrasse 35, 8092 Zurich, Switzerland
ISSN:
0026-2714
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18835140
Database:
PASCAL Archive
Weitere Informationen
In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.