Treffer: Integration of gas cluster process for copper interconnects reliability improvement and process impact evaluation on BEOL dielectric materials

Title:
Integration of gas cluster process for copper interconnects reliability improvement and process impact evaluation on BEOL dielectric materials
Authors:
GRAS, R, GASSET, L. G, FOSSATI, D, LE FRIEC, Y, TORRES, J, HOPSTAKEN, M, BOUYSSOU, R, CHEVOLLEAU, T, PETITPREZ, E, GIRAULT, V, JULLIAN, S, GUILLAN, J, IMBERT, G
Source:
INFOS 2007: Proceedings of the 15th Biennial Conference on Insulating Films on Semiconductors, June 20-23, 2007, Glyfada Athens, GreeceMicroelectronic engineering. 84(9-10):2184-2187
Publisher Information:
Amsterdam: Elsevier Science, 2007.
Publication Year:
2007
Physical Description:
print, 7 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Amélioration procédé, Process improvement, Mejoramiento procedimiento, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Circuit intégré, Integrated circuit, Circuito integrado, Critère performance, Performance requirement, Criterio resultado, Direction cristallographique, Crystallographic direction, Dirección cristalográfica, Diélectrique basse permittivité, Low k dielectric, Dieléctrico baja constante dieléctrica, Défaillance, Failures, Fallo, Dépôt chimique phase vapeur, Chemical vapor deposition, Depósito químico fase vapor, Electrodiffusion, Electrodifusión, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Fiabilité, Reliability, Fiabilidad, Interconnexion, Interconnection, Interconexión, Matériau poreux, Porous material, Material poroso, Optimisation, Optimization, Optimización, Polissage mécanochimique, Chemical mechanical polishing, Semiconducteur type n, n type semiconductor, Semiconductor tipo n, Système autonome, Autonomous system, Sistema autónomo, Système n niveaux, Multilevel system, Sistema n niveles, Technologie avancée, Advanced technology, Tecnología avanzada, CuSiN, USG, electromigration, gas cluster process, integration, interconnects, porous SiOC
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles, France
Laboratoire des Technologies de la Microélectronique, Grenoble, France
NXP Semiconductors, Crolles, France
Freescale Semiconductor, Crolles, France
ISSN:
0167-9317
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18853538
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18853538
Database:
PASCAL Archive

Weitere Informationen

A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.