Result: On-line global energy optimization in multi-core systems using principles of analog computation
Title:
On-line global energy optimization in multi-core systems using principles of analog computation
Authors:
Source:
ESSCIRC 2006IEEE journal of solid-state circuits. 42(7):1593-1606
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 25 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Alimentation électrique, Power supply, Alimentación eléctrica, Basse tension, Low voltage, Baja tensión, Circuit intégré, Integrated circuit, Circuito integrado, Fréquence multiple, Multiple frequency, Frecuencia múltiple, Gestion énergie, Energy management, Gestión energía, Implémentation, Implementation, Implementación, Optimisation, Optimization, Optimización, Processeur, Processor, Procesador, Réponse temporelle, Time response, Respuesta temporal, Résistance électrique, Resistor, Resistencia eléctrica(componente), Système sur puce, System on a chip, Sistema sobre pastilla, Analog computation, System-on-Chip, dynamic voltage and frequency scaling, energy management, on-line energy optimization, pseudo-resistors, translinear loops, weak inversion
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, United States
Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne 1015, Switzerland
Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne 1015, Switzerland
ISSN:
0018-9200
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18943694
Database:
PASCAL Archive
Further Information
This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements on-chip. The optimized voltage/frequency assignments are tailored to the instantaneous workload information on multiple tasks and fully adaptive to variations in process and temperature. The optimizer unit has a response time of less than 50 μs, occupies a silicon area of 0.021 mm2 /task and dissipates 2 mW/task.