• Jitter characteristic in charg...

Treffer: Jitter characteristic in charge recovery resonant clock distribution

Title:
Jitter characteristic in charge recovery resonant clock distribution
Authors:
MESGARZADEH, Behzad, HANSSON, Martin, ALVANDPOUR, Atila
Source:
ESSCIRC 2006IEEE journal of solid-state circuits. 42(7):1618-1625
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Propriétés des circuits, Circuit properties, Circuits hyperfréquences, circuits intégrés hyperfréquences, lignes de transmission hyperfréquences, circuits à ondes submillimétriques, Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits, Chemin données, Data path, Camino datos, Circuit LC, LC circuit, Circuito LC, Electronique faible puissance, Low-power electronics, Essai circuit intégré, Integrated circuit testing, Gigue rythme, Timing jitter, Fluctuación ritmo, Horloge, Clock, Reloj, Reconstitution rythme, Clock recovery, Recuperación de reloj, Résonateur hyperfréquence, Microwave resonator, Resonador hiperfrecuencia, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Traitement pipeline, Pipeline processing, Verrouillage injection, Injection locking, Enganche inyección, Charge recovery resonant clocking, clock distribution network, jitter peaking, jitter suppression, low power
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden
ISSN:
0018-9200
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18943696
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18943696
Database:
PASCAL Archive

Weitere Informationen

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-μm standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.