Result: Improvement of fabrication process for 10-kA/cm2 multi-layer Nb integrated circuits

Title:
Improvement of fabrication process for 10-kA/cm2 multi-layer Nb integrated circuits
Authors:
SATOH, Tetsuro, HINODE, Kenji, NAGASAWA, Shuichi, KITAGAWA, Yoshihiro, HIDAKA, Mutsuo
Source:
The 2006 applied superconductivity conference, Seattle, WA, August 27-September 1, 2006IEEE transactions on applied superconductivity. 17(2):169-172
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 18 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs supraconducteurs, Superconducting devices, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Criblage, Screening, Cernido, Câblage, Wiring, Colocación cables, Densité courant critique, Critical current density, Densidad corriente crítica, Effet Josephson, Josephson effect, Efecto Josephson, Epaisseur couche, Layer thickness, Espesor capa, Fiabilité, Reliability, Fiabilidad, Isolation électrique, Electrical insulation, Aislamiento eléctrico, Jonction Josephson, Josephson junction, Unión Josephson, Ligne transmission, Transmission line, Línea transmisión, Mesure température, Temperature measurement, Medida temperatura, Monitorage, Monitoring, Monitoreo, Multicouche, Multiple layer, Capa múltiple, Pastille électronique, Wafer, Pastilla electrónica, Planarisation, Planarization, Planarización, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Température ambiante, Room temperature, Temperatura ambiente, -Integrated circuit fabrication, Josephson device fabrication, niobium, superconducting integrated circuits
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Superconductivity Research Laboratory, ISTEC, 34, Miyukigaoka, Tsukuba, Ibaraki 305-8501, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010167
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.19010167
Database:
PASCAL Archive

Further Information

-We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current density of Josephson junctions of 10 kA/cm2. We have continued to improve this advanced process. For nine-layer integration, we readjusted film thickness of Nb and SiO2 layers in order to reduce the strain of films and substrate. Total film thickness of the nine-Nb layered structure was about 3 μm; this was kept nearly as thin as that of the six-Nb-layered structure. The resulting thinner SiO2 layers enabled narrower passive transmission line wiring, which had the advantage of smaller occupation area. The room temperature measurement of process monitoring patterns is useful for screening defective wafers in the middle step of the process. For higher circuit reliability, we modified fabrication processes such as junction planarization. As a result, the reliability of SiO2 insulation between an upper and a lower Nb wire adjacent to a Josephson junction was improved.