Result: Scalable matrix multiplication with hybrid CMOS-RSFQ digital signal processor

Title:
Scalable matrix multiplication with hybrid CMOS-RSFQ digital signal processor
Authors:
KATAEVA, Irina, ENGSETH, Henrik, KIDIYAROVA-SHEVCHENKO, Anna
Source:
The 2006 applied superconductivity conference, Seattle, WA, August 27-September 1, 2006IEEE transactions on applied superconductivity. 17(2):486-489
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 15 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Antémémoire, Cache memory, Antememoria, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique supraconducteur, Superconducting logic circuits, Extensibilité, Scalability, Estensibilidad, Horloge, Clock, Reloj, Logique quantique, Quantum logic, Lógica cuántica, Processeur signal numérique, Digital signal processor, Procesador señal numérica, Puce électronique, Chip, Pulga electrónica, Synchronisation, Synchronization, Sincronización, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, DSP, RSFQ, hybrid memory, multiply-accumulate unit
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Microtechnology and Nanoscience Department, Chalmers University of Technology, 41296 Gothenburg, Sweden
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010241
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.19010241
Database:
PASCAL Archive

Further Information

We report an RSFQ Digital Signal Processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ Multiply-Accumulate Unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10 x 10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4 × 4 MAC with rounding to 5 bits and 17 x 6 memory caches has been designed for HYPRES 4.5 kA/cm2 process.