Treffer: A SEU-protected cache memory-based on variable associativity of sets

Title:
A SEU-protected cache memory-based on variable associativity of sets
Authors:
HAMID REZA ZARANDI, SEYED GHASSEM MIREMADI
Source:
SAFECOMP 2004, the 23rd International Conference on Computer Safety, Reliability and SecurityReliability engineering & systems safety. 92(11):1584-1596
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 44 ref
Original Material:
INIST-CNRS
Subject Terms:
Control theory, operational research, Automatique, recherche opérationnelle, Energy, Énergie, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Recherche operationnelle. Gestion, Operational research. Management science, Recherche opérationnelle et modèles formalisés de gestion, Operational research and scientific management, Théorie de la fiabilité. Renouvellement des équipements, Reliability theory. Replacement problems, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Systèmes informatiques et systèmes répartis. Interface utilisateur, Computer systems and distributed systems. User interface, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Antémémoire, Cache memory, Antememoria, Basculement transitoire, Single event upset, Balanceo transitorio, Code correcteur erreur, Error correcting code, Código corrector error, Conception circuit, Circuit design, Diseño circuito, Correction erreur, Error correction, Corrección error, Détection erreur, Error detection, Detección error, Energétique, Energetics, Energética, Fiabilité, Reliability, Fiabilidad, Haute performance, High performance, Alto rendimiento, Modélisation, Modeling, Modelización, Temps rupture, Break up time, Tiempo ruptura, Associativité, Associativity, Asociatividad, Injection faute, Fault injection, Inyección falta, Mémoire accès direct statique, Static random access memory, Memoria Estática de Acceso Aleatorio
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Computer Engineering, Sharif University of Technology, P.O. Box 11365-9517, Tehran, Iran, Islamic Republic of
ISSN:
0951-8320
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010723
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics

Operational research. Management
Accession Number:
edscal.19010723
Database:
PASCAL Archive

Weitere Informationen

SRAM cache memories suffer from single event upset (SEU) faults induced by energetic particles such as neutron and alpha particles. To protect these caches, designers often use error detection and correction codes, which typically provide single-bit error detection and even correction. However, these codes have low error detection capability or incur significant performance penalties. In this paper, a protected cache scheme based on the variable associativity of sets is presented. In this scheme, cache space is divided into sets of different sizes with variable tag field lengths. The other remained bits of tags are used for protecting the tag using a new protection code. This leads to protect the cache without compromising performance and area with respect to the similar one, fully associative cache. The scheme provides high SEU detection coverage as well as high performance. Moreover, reliability and mean-time-to-failure (MTTF) equations are derived and estimated. The results obtained from fault injection experiments and several trace files from SPEC2000 reveal that the proposed scheme exhibits a good performance near to fully associative cache but can detect high percent of SEU faults.