Result: Memory management optimization problems for integrated circuit simulators
Title:
Memory management optimization problems for integrated circuit simulators
Authors:
Source:
3rd Cologne/Twente Workshop on Graphs and Combinatorial OptimizationDiscrete applied mathematics. 155(14):1795-1811
Publisher Information:
Amsterdam; Lausanne; New York, NY: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 18 ref
Original Material:
INIST-CNRS
Subject Terms:
Control theory, operational research, Automatique, recherche opérationnelle, Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences et techniques communes, Sciences and techniques of general use, Mathematiques, Mathematics, Combinatoire. Structures ordonnées, Combinatorics. Ordered structures, Combinatoire, Combinatorics, Plans d'expériences et configurations, Designs and configurations, Analyse mathématique, Mathematical analysis, Calcul des variations et contrôle optimal, Calculus of variations and optimal control, Analyse numérique. Calcul scientifique, Numerical analysis. Scientific computation, Analyse numérique, Numerical analysis, Méthodes numériques en programmation mathématique, optimisation et calcul variationnel, Numerical methods in mathematical programming, optimization and calculus of variations, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Algorithmique. Calculabilité. Arithmétique ordinateur, Algorithmics. Computability. Computer arithmetics, Arbre graphe, Tree(graph), Arbol grafo, Circuit intégré, Integrated circuit, Circuito integrado, Code, Código, Combinatoire, Combinatorics, Combinatoria, Complexité, Complexity, Complejidad, Comportement, Behavior, Conducta, Conception, Design, Diseño, Digraphe, Digraph, Digrafo, Fonction coût, Cost function, Función coste, Gestion, Management, Gestión, Graphe acyclique, Acyclic graph, Grafo acíclico, Graphe orienté, Directed graph, Grafo orientado, Informatique théorique, Computer theory, Informática teórica, Minimisation, Minimization, Minimización, Modèle mathématique, Mathematical model, Modelo matemático, Mémoire, Memory, Memoria, Méthode optimisation, Optimization method, Método optimización, Optimisation, Optimization, Optimización, Problème NP complet, NP complete problem, Problema NP completo, Procédure, Procedure, Procedimiento, Relation ordre, Ordering, Relación orden, Simulation, Simulación, Temps accès, Access time, Tiempo acceso, Temps polynomial, Polynomial time, Tiempo polinomial, 05Bxx, 05C05, 05C20, 49XX, 51E24, 65Kxx, 68R10, Temps cycle, Cycle time, Graph ordering, Integrated circuit simulation
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
LIP6 -Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France
ISSN:
0166-218X
Rights:
Copyright 2008 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Mathematics
Mathematics
Accession Number:
edscal.19046561
Database:
PASCAL Archive
Further Information
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator. An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.