Result: Adapting compilation techniques to enhance the packing of instructions into registers

Title:
Adapting compilation techniques to enhance the packing of instructions into registers
Authors:
HINES, Stephen, WHALLEY, David, TYSON, Gary
Source:
CASES 2006 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 22-25, 2006, Seoul, Korea, embedded systems week 2006). :43-53
Publisher Information:
New York NY: ACM Press, 2006.
Publication Year:
2006
Physical Description:
print, 23 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Théorie des langages et analyse syntaxique, Language theory and syntactical analysis, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Calculateur embarqué, Boarded computer, Calculador embarque, Code temps, Time code, Código tiempo, Commercialisation, Marketing, Comercialización, Compilateur optimisation, Optimizing compilers, Compilation, Compilación, Conception architecturale, Architectural design, Concepción arquitectural, Consommation énergie, Energy consumption, Consumo energía, Economies d'énergie, Energy savings, Ahorros energía, Méthode heuristique, Heuristic method, Método heurístico, Optimisation compilateur, Compiler optimization, Optimización compiladora, Optimisation programme, Program optimization, Optimización programa, Ordonnancement, Scheduling, Reglamento, Temps exécution, Execution time, Tiempo ejecución, Fichier registre, Register file, Fichero registro
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Stephen mines, David Whalley, Gary Tyson Computer Science Department Florida State University, Tallahassee, FL 32306-4530, United States
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19105481
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.19105481
Database:
PASCAL Archive

Further Information

The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Traditional compiler optimizations are often tuned for improving general architectural constraints, yet these heuristics may not be as beneficial to less conventional designs. Instruction packing is a recently developed compiler/architectural approach for reducing energy consumption, code size, and execution time by placing the frequently occurring instructions into an Instruction Register File (IRF). Multiple IRF instructions are made accessible via special packed instruction formats. This paper presents the design and analysis of a compilation framework and its associated optimizations for improving the efficiency pf instruction packing. We show that several new heuristics can be developed for IRF promotion, instruction selection, register re-assignment and instruction scheduling, leading to significant reductions in energy consumption, code size, and/or execution time when compared to results using a standard optimizing compiler targeting the IRF.