Treffer: Incremental elaboration for run-time reconfigurable hardware designs

Title:
Incremental elaboration for run-time reconfigurable hardware designs
Authors:
DERBYSHIRE, Arran, BECKER, Tobias, LUK, Wayne
Source:
CASES 2006 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 22-25, 2006, Seoul, Korea, embedded systems week 2006). :93-102
Publisher Information:
New York NY: ACM Press, 2006.
Publication Year:
2006
Physical Description:
print, 23 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Intelligence artificielle, Artificial intelligence, Reconnaissance des formes. Traitement numérique des images. Géométrie algorithmique, Pattern recognition. Digital image processing. Computational geometry, Appariement image, Image matching, Architecture reconfigurable, Reconfigurable architectures, Calculateur embarqué, Boarded computer, Calculador embarque, Circuit à la demande, Custom circuit, Circuito integrato personalizado, Compilateur, Compiler, Compilador, Compilation, Compilación, Conception circuit, Circuit design, Diseño circuito, Concordance forme, Pattern matching, Contrôle déformation mécanique, Strain control, Microprocesseur, Microprocessor, Microprocesador, Modélisation, Modeling, Modelización, Métamodèle, Metamodel, Metamodelo, Méthode adaptative, Adaptive method, Método adaptativo, Reconnaissance objet, Object recognition, Réutilisation, Reuse, Reutilización, Traitement image, Image processing, Procesamiento imagen, Patron conception, Design pattern, Patrón Concepción
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Computing, Imperial College London 180 Queen's Gate, London SW7 2BZ, United Kingdom
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19105486
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.19105486
Database:
PASCAL Archive

Weitere Informationen

We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant run-time overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching.